Arm Slave

Views Updated: Dec 15, 2025

Abbreviation

Pronunciation

/ɑrm sleɪv/

Because of the specialties of the IP design, driver designer should consider the route switch between the high-speed and the full speed controller, access to shared buffer, and the mode of ARM accessing the IP core as a slave.
By using ARM + DSP master slave system, embedded uC / OS - ⅱ and reasonable task-assigned strategy, the real-time of the system were guaranteed.
This paper introduced a method of using ARM microprocessor to configure FPGA in slave serial in embedded system. System program and configuration data were stored in Flash, the timing was generated by ARM general IO, the dedicated configuration PROM were reduced.
In the SOC, 3 master buses are connected with DATA, INST of ARM core, and system DAM bus, and 8 slave buses are connected with some peripheral buses and external memories.
The hardware of master and slave modules uses embedded ARM processor with CAN controller as their core CPU and uses the real time operating system & μ C / OS - ⅱ as their software designing platform.

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